The present invention relates to integrated circuit devices and methods of forming the same, and more particularly, to integrated circuit devices with capacitors and methods of forming the same.
As the level of integration in integrated circuit memory devices has increased, much research and development has been directed toward reducing effective cell area. In these efforts, the unit area available for capacitor formation has decreased, thus creating a need for increased capacitance per unit area.
There are several conventional techniques for obtaining sufficient capacitance. One technique is to modify the widely used cylinder structure to increase dielectric area. A second technique is to employ a dielectric layer having a high dielectric constant. For example, a conventional DRAM (dynamic random access memory) may employ a capacitor with an MIS (metal/insulator/silicon) or an MIM (metal/insulator/metal) structure with a dielectric layer including tantalum oxide (Ta2O5) or BST [(Ba,Sr)TiO3] having a higher dielectric constant than a triple layer of oxide/nitride/oxide, which may be used as a dielectric layer of an SIS (silicon/insulator/silicon) structure. A third technique is to reduce the thickness of a dielectric layer using materials such as tantalum oxide.
An SIS or MIS structure employing polysilicon as an electrode material may be fabricated relatively easily. Additionally, an SIS or MIS structure can typically be fabricated using existing processes. However, when an electric field is applied to an SIS or MIS structure, a depletion area typically is formed in the polysilicon, and this depletion area and the insulator are connected parallel to each other, which can thereby decrease the entire capacitance. Additionally, when polysilicon layer is used as a bottom electrode in the structure, an oxide may form at a surface of the bottom electrode of the polysilicon, which can increase the total thickness of the dielectric layer. This can decrease the total capacitance.
However, in a conventional MIM structure that employs metal electrodes, there typically is neither formation of a depletion layer nor a decrease of capacitance due to the depletion layer. Additionally, a typical MIM structure is typically less vulnerable to electrode oxidation. However, an MIM structure may be difficult to fabricate using existing processes.
A typical DRAM device having an MIM structure includes a buried contact plug that connects the capacitor of the MIM structure to a transistor on a semiconductor substrate. The buried contact plug is typically formed of polysilicon, because polysilicon generally has a superior gap-fill characteristic and because resistance of polysilicon can generally be easily controlled. When a DRAM device includes a buried contact plug of polysilicon and a capacitor having an MIM structure, the DRAM device typically also includes an ohmic layer that is used to overcome resistance between the polysilicon and the metal. Additionally, the DRAM device may employ a barrier layer in order to prevent the buried contact plug from being oxidized. However, conventional processes for forming the ohmic layer and the barrier layer between the buried contact plug and the metal bottom electrode may be complex, involving recess and planarization steps.